In recent years, with the advances in semiconductor miniaturization technologies, densities and capacities of memory devices (memories) have been significantly increased. The field of nonvolatile memory devices has made remarkable technological developments in flash memories and electrically erasable and programmable ROMs (EEPROMs), and thus begun to achieve cost reduction. In particular, the cost of flash memories has been reduced year after year. Under these circumstances, a system employing a flash memory has been used in many fields from a field of program storage devices to be built into home electrical appliances to a field of data storage devices for storing data including music, images, and video. With a further cost reduction, nonvolatile memory devices can be expected to be applied in various fields. The miniaturization and cost reduction of conventional nonvolatile memory devices have been implemented by the advances in the technologies for manufacturing flash memories. In recent years, however, the miniaturization of flash memories employing floating gates is said to be approaching the limit. With this being the situation, a new nonvolatile memory device has received attention for further reducing a cell area size and a cost.
Research and development have been promoted for a nonvolatile memory device, as the new nonvolatile memory device, having a memory cell including a variable resistance element. Here, the variable resistance element reversibly changes a resistance value in response to an electrical signal, and can store data corresponding to this resistance value in a nonvolatile manner.
As a nonvolatile memory device employing a variable resistance element, a 1T1R nonvolatile memory device is generally known. This 1T1R nonvolatile memory device has a structure where so-called 1T1R memory cells are arranged in an array of a matrix. Each of the 1T1R memory cells includes a metal oxide semiconductor (MOS) transistor and a variable resistance element that are connected in series at a position near a cross point of a bit line and a word line that are arranged to cross each other. In the 1T1R memory cell, one terminal of the two-terminal variable resistance element is connected to the bit line or a source line, and the other terminal is connected to a drain terminal or a source terminal of the transistor. A gate terminal of the transistor is connected to the word line. The source line is set in parallel to the bit line or the word line.
Moreover, as another example, a cross point nonvolatile memory device is also generally known (see Patent Literatures 1 and 2, for instance). This cross point nonvolatile memory device has a memory cell structure where so-called 1D1R memory cells are arranged in an array of a matrix. Each of the 1D1R memory cells includes a diode serving as a current steering element and a variable resistance element that are connected in series at a cross point of a bit line and a word line that are arranged to cross each other.
Patent Literature 1 discloses a 1D1R nonvolatile memory device that employs, as a memory cell, a variable resistance element having a characteristic of changing resistance bidirectionally. FIG. 17 is a diagram showing a configuration of a conventional nonvolatile memory cell. FIG. 17 shows a memory cell array having a cross point structure where a memory cell 1280 is placed at a cross point of a bit line 1210 and a word line 1220. The memory cell 1280 includes a variable resistance element 1260 and a nonlinear element 1270 that are connected in series. The variable resistance element 1260 includes a variable resistor 1230 sandwiched between an upper electrode 1240 and a lower electrode 1250. Here, the variable resistance element 1260 has a characteristic of reversibly changing a resistance value between a low resistance state and a high resistance state bidirectionally, in response to a polarity of the applied voltage. Moreover, the nonlinear element 1270 is configured with, for example, a varistor for the purpose of reducing a leakage current, as it is called, that passes through a nonselected cell. In the memory cell array having the cross point structure, the memory cells can be arranged according to a wiring pitch. Furthermore, such memory cell arrays can be stacked three-dimensionally, thereby increasing in capacity.
Patent Literature 2 discloses a method of detecting a fault in a nonlinear element included in a 1D1R memory cell that is configured with a unidirectional variable resistance element. FIG. 18 is a diagram showing a configuration of a conventional nonvolatile memory cell array. In FIG. 18, a memory cell is placed at each cross point of bit lines BL1, BL2, and BL3 and word lines WL1, WL2, and WL3. The memory cell includes a unidirectional variable resistance element and a unidirectional diode element that are connected in series. The unidirectional diode has an anode and a cathode. With the application of a potential “Vdd” to all the bit lines and the application of a potential “Vss” to all the word lines, no current passes through a normal diode element in a reverse biased state. However, a DC current passes through a faulty diode element even in the reverse biased state, and the bit line on which the faulty diode element is located decreases in potential from the potential Vdd. Patent Literature 2 discloses a method of detecting a bit line having such a faulty diode element as a faulty bit line. FIG. 19 is a diagram showing a model of a memory cell employing a conventional unidirectional diode. As shown in FIG. 19, a fault detection circuit 2053 described in Patent Literature 2 includes a bit-line power supply circuit 2054, a latch circuit 2531, and a switch circuit 2055, and is connected to a bit line connected to a bit line selection circuit 2024. A standby unit 2052 of the fault detection circuit 2053 detects a faulty bit line connected to a faulty diode element.